Reducing instruction fetch energy with backwards branch control information and buffering

Many emerging applications, e.g. in the embedded and DSP space, are often characterized by their loopy nature where a substantial part of the execution time is spent within a few program phases. Loop buffering techniques have been proposed for capturing and processing these loops in small buffers to reduce the processor‘s instruction fetch energy. However, these schemes are limited to straight-line or inner-most loops and fail to adequately handle complex loops. In this paper, we propose a dynamic loop buffering mech-anism that uses backwards branch control information to identify, capture and process complex loop structures. The DLB controller has been fully implemented in VHDL, syn-thesized and timed with the IBM Booledozer and Einstimer Synthesis tools, and analyzed for power with the Sequence PowerTheater tool. Our experiments show that the DLB approach, on average, results in a factor of 3 reduction in energy consumption compared to a traditional instruction memory design at an area overhead of about 9%

Locative Media and Sociability:Using Location-Based Social Networks to Coordinate Everyday Life

Foursquare was a mobile social networking application that enabled people to share location with friends in the form of “check-ins.” The visualization of surrounding known social connections as well as unknown others has the potential to impact how people coordinate social encounters and forge new social ties. While many studies have explored mobile phones and sociability, there is a lack of empirical research examining location-based social network’s (LSBNs) from a sociability perspective. Drawing on a dataset of original qualitative research with a range of Foursquare users, the paper examines the application in the context of social coordination and sociability in three ways. First, the paper explores if Foursquare is used to organize certain social encounters, and if so, why. Second, the paper examines the visualization of surrounding social connections and whether this leads to “serendipitous encounters.” Lastly, the paper examines whether the use of Foursquare can produce new social relationships

Genomic investigations of unexplained acute hepatitis in children

Since its first identification in Scotland, over 1,000 cases of unexplained paediatric hepatitis in children have been reported worldwide, including 278 cases in the UK1. Here we report an investigation of 38 cases, 66 age-matched immunocompetent controls and 21 immunocompromised comparator participants, using a combination of genomic, transcriptomic, proteomic and immunohistochemical methods. We detected high levels of adeno-associated virus 2 (AAV2) DNA in the liver, blood, plasma or stool from 27 of 28 cases. We found low levels of adenovirus (HAdV) and human herpesvirus 6B (HHV-6B) in 23 of 31 and 16 of 23, respectively, of the cases tested. By contrast, AAV2 was infrequently detected and at low titre in the blood or the liver from control children with HAdV, even when profoundly immunosuppressed. AAV2, HAdV and HHV-6 phylogeny excluded the emergence of novel strains in cases. Histological analyses of explanted livers showed enrichment for T cells and B lineage cells. Proteomic comparison of liver tissue from cases and healthy controls identified increased expression of HLA class 2, immunoglobulin variable regions and complement proteins. HAdV and AAV2 proteins were not detected in the livers. Instead, we identified AAV2 DNA complexes reflecting both HAdV-mediated and HHV-6B-mediated replication. We hypothesize that high levels of abnormal AAV2 replication products aided by HAdV and, in severe cases, HHV-6B may have triggered immune-mediated hepatic disease in genetically and immunologically predisposed children

Processor modeling and evaluation techniques for early design stage performance comparison.

This thesis develops two techniques and a design space search hierarchy that can be used to examine a large space of processor designs early in the design cycle, before an expensive investment has been made on hardware design, allowing designers to select an initial processor design that will satisfy more of the processor's design goals, reducing the number and cost of the design iterations. They also allow the designers to investigate the impact of trade-offs in the processor design, better preparing the project for later changes required in order for the processor to meet its area, power, or other design constraints. The first technique is the resource conflict methodology (RCM), a full execution trace driven simulation that allows specification of the processor organization, design parameters and even the instruction set architecture model, and performance is estimated as accurately as a traditional (cycle-by-cycle) simulator for the same processor model. The resource conflict methodology therefore provides the user the flexibility to examine a large number of different processor designs, but simulation time can be limiting because RCM is driven by a full execution trace. The second technique, called reduced trace analysis (RTA), addresses the simulation time problem by reducing the redundant calculation done while generating a performance estimate. RTA analyzes the trace to develop a weighted control-flow graph representation of the execution of the workload, where each node represents a sequentially-executed code block and each weighted, directed link represents a number of transfers of control between the linked blocks during execution. RTA uses a trace simulator to derive estimates for each code block and each interface between connected blocks, then weights and assembles these estimates to determine the full performance estimate. This method significantly reduces the simulation time for each processor model, and yet still produces estimates within a few percent of the RCM estimates. Thus, RTA allows the user to investigate a large number of designs much more quickly than full trace simulation methods.Ph.D.Applied SciencesComputer scienceElectrical engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/130159/2/9712120.pd

Exploring real time multimedia content creation in video games

Video games represent a class of media applications for which creating video content is as important as displaying it. In this paper, we compare video games running on an Apple Macintosh G5 to DVD playback and the QuickTime media player. We use performance monitor counters to find the IPC, the L1 data cache miss rate and the AGP and processor memory bandwidth. We find the frame-oriented nature of all of these applications reflected in many of the metrics used in this study. Video game applications exhibit significantly less idle time between updates to the screen than DVD playback and QuickTime. The results also show that adding computer controlled characters to a video game further reduces the idle time, and causes a decrease in the L2 cache pressure, spreading the access misses over a longer time period. 1

Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor

We describe a new power-performance modeling toolkit, developed to aid in the evaluation and definition of future power-efficient, PowerPC TM processors. The base performance models in use in this project are: (a) a fast but cycle-accurate, parameterized research simulator and (b) a slower, pre-RTL reference model that models a specific high-end machine in full, latchaccurate detail. Energy characterizations are derived from real, circuit-level power simulation data. These are then combined to form higher-level energy models that are driven by microarchitecture-level parameters of interest. The overall methodology allows us to conduct power-performance tradeoff studies in defining the follow-on design points within a given product family. We present a few experimental results to illustrate the kinds of tradeoffs one can study using this tool